? semiconductor components industries, llc, 2006 june, 2006 ? rev. 6 1 publication order number: MC14598B/d MC14598B 8?bit bus?compatible latches the MC14598B is an 8?bit latch addressed with an external binary address. the 8 latch?outputs are high drive, three?state and bus line compatible. the drive capability allows direct applications with mpu systems such as the motorola 6800 family. the latches of the MC14598B are accessed via the address pins, a0, a1, and a2. all 8 outputs from the latches are available in parallel when enable is in the low state. data is entered into a selected latch from the data pin when the strobe is high. master reset is available on both parts. features ? serial data input ? three?state bus compatible parallel outputs ? three?state control pin (enable ) ttl compatible input ? open drain full flag (multiple latch wire?o ring) ? master reset ? level shifting inputs on all except enable ? diode protection ? all inputs ? supply voltage range ? 3.0 vdc to 18 vdc ? capable of driving ttl over rated temperature range with fanout as follows: 1 ttl load 4 lsttl loads ? pb?free package is available* maximum ratings (voltages referenced to v ss ) parameter symbol value unit dc supply voltage range v dd ?0.5 to +18.0 v input voltage range, enable (dc or transient) v in ?0.5 to v dd +0.5 v input voltage range, all other inputs (dc or transient) v in ?0.5 to v dd +12 v output voltage range, (dc or transient) v out ?0.5 to v dd +0.5 v input or output current (dc or transient) per pin i in , i out 10 ma power dissipation per package (note 1) p d 500 mw ambient temperature range t a ?55 to +125 c storage temperature range t stg ?65 to +150 c lead temperature (8?second soldering) t l 260 c stresses exceeding maximum ratings may damage the device. maximum ratings are stress ratings only. functional operation above the recommended operating conditions is not implied. extended exposure to stresses above the recommended operating conditions may affect device reliability. 1. temperature derating: plastic ?p and d/dw? packages: ? 7.0 mw/ c from 65 c to 125 c *for additional information on our pb?free strategy and soldering details, please download the on semiconductor soldering and mounting techniques reference manual, solderrm/d. a = assembly location wl = wafer lot yy = year ww = work week g = pb?free package device package shipping ordering information MC14598Bcp pdip?18 20 units/rail marking diagram 1 18 pdip?18 p suffix case 707 MC14598Bcp awlyywwg MC14598Bcpg pdip?18 (pb?free) 20 units/rail http://onsemi.com this device contains protection circuitry to guard against damage due to high static voltages or electri c fields. however, precautions must be taken to avoid applications of any voltage higher than maximum rated voltages to this high?impedance circuit. fo r proper operation, v in and v out should be constrained to the range v ss (v in or v out ) v dd . unused inputs must always be tied to an appropriate logic voltage level (e.g., either v ss o r v dd ). unused outputs must be left open. 1 enable outputs 1 high impedance 0d n d n = state of nth latch output truth table nc = no connection
MC14598B http://onsemi.com 2 pin assignment nc data reset d0 v ss a1 a0 strobe enable d3 d2 d1 v dd a2 d7 d6 d5 d4 14 15 16 17 18 10 11 12 13 5 4 3 2 1 9 8 7 6 block diagram 1 17 16 15 14 13 12 11 d0 d1 d2 d3 d4 d5 d6 d7 enable 4 three state output buffers 8 latches address decoder v dd = 18 v ss = 9 2 3 6 reset data strobe a0 a1 a2 7 8 10 ????????????????????????????????? ????????????????????????????????? electrical characteristics (voltages referenced to v ss ) characteristic symbo l v dd v dc ? 55 c 25 c 125 c unit min max min typ (note 2) max min max output voltage ?0? level v in = v dd or 0 v ol 5.0 10 15 ? ? ? 0.05 0.05 0.05 ? ? ? 0 0 0 0.05 0.05 0.05 ? ? ? 0.05 0.05 0.05 vdc ?1? level v in = 0 or v dd v oh 5.0 10 15 4.95 9.95 14.95 ? ? ? 4.95 9.95 14.95 5.0 10 15 ? ? ? 4.95 9.95 14.95 ? ? ? vdc input voltage (note 3), enable ?0? level (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 ? ? ? 0.8 1.6 2.4 ? ? ? 1.1 2.2 3.4 0.8 1.6 2.4 ? ? ? 0.8 1.6 2.4 vdc ?1? level (v o = 0.5 or 4.5 vdc) (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 2.0 6.0 10 ? ? ? 2.0 6.0 10 1.9 3.1 4.3 ? ? ? 2.0 6.0 10 ? ? ? vdc input voltage ?0? level other inputs (v o = 4.5 or 0.5 vdc) (v o = 9.0 or 1.0 vdc) (v o = 13.5 or 1.5 vdc) v il 5.0 10 15 ? ? ? 1.5 3.0 4.0 ? ? ? 2.25 4.50 6.75 1.5 3.0 4.0 ? ? ? 1.5 3.0 4.0 vdc (v o = 0.5 or 4.5 vdc) ?1? level (v o = 1.0 or 9.0 vdc) (v o = 1.5 or 13.5 vdc) v ih 5.0 10 15 3.5 7.0 11 ? ? ? 3.5 7.0 11 2.75 5.50 8.25 ? ? ? 3.5 7.0 11 ? ? ? vdc output drive current source (full ? sink only) (v oh = 4.6 vdc) (v oh = 9.5 vdc) (v oh = 13.5 vdc) i oh 5.0 10 1 5 ?1.0 ? ? ? ? ? ?1.0 ? ? ?2.0 ?6.0 ?12 ? ? ? ?1.0 ? ? ? ? ? madc (v ol = 0.4 vdc) sink (v ol = 0.5 vdc) (v ol = 1.5 vdc) i ol 5.0 10 15 1.6 ? ? ? ? ? 1.6 ? ? 3.2 6.0 12 ? ? ? 1.6 ? ? ? ? ? madc input current i in 15 ? 0.1 ? 0.00001 0.1 ? 1.0 adc 3?state leakage current i tl 15 ? 0.1 ? 0.00001 0.1 ? 3.0 adc input capacitance (v in = 0) c in ? ? ? ? 5.0 7.5 ? ? pf quiescent current (per package) i dd 5.0 10 15 ? ? ? 5.0 10 20 ? ? ? 0.005 0.010 0.015 5.0 10 20 ? ? ? 150 300 600 adc total supply current at an external load capacitance of 130 pf (note 3) i t 5.0 10 i t = (2.0 a/khz) f + i dd i t = (4.0 a/khz) f + i dd i t = (6.0 a/khz) f + i dd adc 2. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance. 3. the formulas given are for the typical characteristics only at 25 c.
MC14598B http://onsemi.com 3 ????????????????????????????????? ????????????????????????????????? (note 4) (t a = 25 c, c l = 130 pf + 1 ttl load) characteristic symbol v dd vdc all types unit min typ (note 5) max output rise and fall time t tlh , t thl = (0.5 ns/pf) c l + 35 ns t tlh , t thl = (0.2 ns/pf) c l + 25 ns t tlh , t thl = (0.16 ns/pf) c l + 20 ns t tlh , t thl 5.0 10 15 ? ? ? 100 50 40 200 100 80 ns propagation delay time enable to output t plh , t phl 5.0 10 15 ? ? ? 160 125 100 320 250 200 ns strobe to output 5.0 10 15 ? ? ? 200 100 80 400 200 160 reset to output 5.0 10 15 ? ? ? 175 90 70 350 180 140 pulse width enable t wh , t wl 5.0 10 15 320 240 160 160 120 80 ? ? ? ns strobe 5.0 10 15 200 100 80 100 50 40 ? ? ? increment 5.0 10 15 200 100 80 100 50 40 ? ? ? reset 5.0 10 15 300 160 100 150 80 50 ? ? ? setup time data t su 5.0 10 15 100 50 35 50 25 20 ? ? ? ns address 5.0 10 15 200 100 70 100 50 35 ? ? ? hold time data t h 5.0 10 15 100 50 35 50 25 20 ? ? ? ns address 5.0 10 15 100 50 35 50 25 20 ? ? ? reset removal time t rem 5.0 10 15 20 20 20 ? 25 ? 15 ? 10 ? ? ? ns 4. the formulas given are for the typical characteristics only at 25 c. 5. data labelled ?typ? is not to be used for design purposes but is intended as an indication of the ic?s potential performance.
MC14598B http://onsemi.com 4 MC14598B function diagram enable 4 reset 2 strobe6 data3 to other latches v dd v ss each latch zero select 1d0 17d1 16d2 15d3 14d4 13d5 12d6 11d7 address decoder additional 7 latches a07 a18 a210 to other latches (m.s.b) MC14598B timing diagram *1.4 v with v dd = 5.0 v notes: 1. high?impedance output state (another device controls bus). 2. output load as for mc14597b. d7 reset a0, a1, a2 data strobe enable 90% 10% 50% 50% t phl t plh 1 t thl t plh 90% 10% t tlh t w 50% 20 ns 90% 10% t su t h t h t su 90% 10% 50% 90% 10% 20 ns t w 20 ns t w *
MC14598B http://onsemi.com 5 truth table for mc14597b address increment enable reset counter full x 1 count up ? x 1 no change ? x 1 0 reset to zero set to one x 0 1 no change set to one if at to zero on x 1 1 address 7 falling edge of strobe x = don?t care latch truth table address other strobe reset latch latches 01 * * 1 1 data * x000 *= no change in state of latch x = don?t care test load, all outputs d n +5.0 v r l = 2.5 k 11.7 k 130 pf circuit diagrams external to or containing motorola products are included as a means of illustration only. complete information sufficient for construction purposes may not be fully illustrated. although the information herein has been carefully checked and is believed to be reliable. motorola assumes no responsibility for inaccuracies. information herein does not convey to the purchaser any license under the patent rights of motorola or others. the information contained herein is for guidance only, with no warranty of any type, expressed or implied. motorola reserves the right to make any changes to the information and the product(s) to which the information applies and to discontinue manufacture of the product(s) at any time.
MC14598B http://onsemi.com 6 package dimensions notes: 1. positional tolerance of leads (d), shall be within 0.25 mm (0.010) at maximum material condition, in relation to seating plane and each other. 2. dimension l to center of leads when formed parallel. 3. dimension b does not include mold flash. 4. controlling dimension: inch. 1 seating plane 10 9 18 m a b k c n f g d h j l dim min max min max millimeters inches a 22.22 23.24 0.875 0.915 b 6.10 6.60 0.240 0.260 c 3.56 4.57 0.140 0.180 d 0.36 0.56 0.014 0.022 f 1.27 1.78 0.050 0.070 g 2.54 bsc 0.100 bsc h 1.02 1.52 0.040 0.060 j 0.20 0.30 0.008 0.012 k 2.92 3.43 0.115 0.135 l 7.62 bsc 0.300 bsc m 0 15 0 15 n 0.51 1.02 0.020 0.040 pdip?18 case 707?02 issue d on semiconductor and are registered trademarks of semiconductor components industries, llc (scillc). scillc reserves the right to mak e changes without further notice to any products herein. scillc makes no warranty, representation or guarantee regarding the suitability of its products for an y particular purpose, nor does scillc assume any liability arising out of the application or use of any product or circuit, and specifically disclaims any and all liability, including wi thout limitation special, consequential or incidental damages. ?typical? parameters which may be provided in scillc data sheets and/or specifications can and do vary in different application s and actual performance may vary over time. all operating parameters, including ?typicals? must be validated for each customer application by customer?s technical experts. scillc does not convey any license under its patent rights nor the rights of others. scillc products are not designed, intended, or authorized for use as components in systems intended for surgical implant into the body, or other applications intended to support or sustain life, or for any other application in which the failure of the scillc product could create a sit uation where personal injury or death may occur. should buyer purchase or use scillc products for any such unintended or unauthorized application, buyer shall indemnify and hold scillc and its of ficers, employees, subsidiaries, affiliates, and distributors harmless against all claims, costs, damages, and expenses, and reasonable attorney fees arising out of, direct ly or indirectly, any claim of personal injury or death associated with such unintended or unauthorized use, even if such claim alleges that scillc was negligent regarding the design or manufacture of the part. scillc is an equal opportunity/affirmative action employer. this literature is subject to all applicable copyright laws and is not for resale in any manner. publication ordering information n. american technical support : 800?282?9855 toll free usa/canada europe, middle east and africa technical support: phone: 421 33 790 2910 japan customer focus center phone: 81?3?5773?3850 MC14598B/d literature fulfillment : literature distribution center for on semiconductor p.o. box 5163, denver, colorado 80217 usa phone : 303?675?2175 or 800?344?3860 toll free usa/canada fax : 303?675?2176 or 800?344?3867 toll free usa/canada email : orderlit@onsemi.com on semiconductor website : www.onsemi.com order literature : http://www.onsemi.com/orderlit for additional information, please contact your local sales representative
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